The present invention relates to a semiconductor device.
A semiconductor device having a concavity at a surface of a silicon substrate of a flow sensor, a thin dielectric film provided at the silicon substrate surface so as to cover this concavity, and a resistor element of a predetermined shape formed on this dielectric film has been disclosed by, for example, Japanese Patent Publication No. TOKUKOUHEI 3-52028.
The semiconductor device having above structure is manufactured by forming a dielectric film on the surface of the silicon substrate and then forming a concavity thereon. The device may be manufactured by a method of etching the silicon substrate from the backside surface (the surface on which dielectric film is not formed) or a method of forming an etching hole for etching the silicon substrate through the dielectric film and then causing etching solution to penetrate through this etching hole to etch the silicon substrate.
In the latter method, because the shape of etching hole formed through the dielectric film greatly affects to the productivity and characteristics of the device including etching time and effective region, careful attention must be paid to the designing of the etching hole. Conventionally, such a shape has generally been a pattern directed toward 45xc2x0 relative to  less than 110 greater than  for a silicon wafer having a (100) surface and  less than 110 greater than  direction.
In a conventional semiconductor device (sensor) having a dielectric film, when an etching hole is formed to etch silicon on the dielectric film surface, because the resistor element or thermoelectric conversion element to be formed on the dielectric film can neither be formed efficiently nor over a wide range at the place where the etching hole has been formed, high output has been prevented. Furthermore, because thermal insulation property is deteriorated, a problem of output voltage drop is also caused.
In addition, the etching hole is normally oriented at a 45xc2x0 tilt relative to  less than 110 greater than  and formed in parallel with the  less than 100 greater than . In this case, the etching hole region becomes large with respect to the entire membrane, and device wiring becomes complicated.
Furthermore, under the conventional etching pattern, the device is not formed in parallel with dicing directions of the device, but is generally tilted by 45xc2x0, it becomes necessary to tilt the device during mounting. As a result, operating efficiency becomes worsened.
This invention has been made taking into consideration of the above mentioned circumstances. The object of the present invention is to provide a semiconductor device that is capable of solving the above mentioned problems, simplifying the wiring pattern, improving yield, lowering resistivity of the wiring, and attaining miniaturization, wherein the device can be readily formed with good efficiency, and manufacture of the concavity can be performed over a short time period by etching via an etching hole.
In order to achieve the above mentioned object, the semiconductor device according to the present invention comprises a semiconductor substrate having a (100) surface and  less than 110 greater than  direction and a concavity formed by anisotropic etching on a surface that is parallel with the (100) surface, a dielectric film provided on the semiconductor substrate so as to cover the concavity, and a circuit pattern having at least one of a resistor element and a thermoelectric conversion element in a predetermined shape formed on the dielectric film. The dielectric film facing the concavity is provided with a first etching hole extending in the  less than 110 greater than  direction of the semiconductor substrate, and a second etching hole extending in the  less than xe2x88x92110 greater than  direction of the semiconductor substrate. The first and second etching holes are formed such that these holes have a side tilted with respect to the  less than 110 greater than  and  less than xe2x88x92110 greater than  (In the implemented embodiment, the side corresponds to xe2x80x9cshorter sides 16b, 17b, and tilted sides 16c, 17c, or tilted sides of a trapezoidxe2x80x9d) and imaginary rectangles passing through the apexes of the first and second etching holes are directly or indirectly continuous.
The etching rates in the direction toward the faces along the  less than 110 greater than  direction and  less than xe2x88x92110 greater than  directions are low. Therefore, for example, if etching is carried out of a rectangular pattern extending in these directions, etching progresses only toward the substrate interior, i.e., toward the (100) surface. For this reason, a conventional etching hole has been given a pattern morphology that extends in directions at 45xc2x0 relative to the  less than 110 greater than  direction. The inventors of the present invention tested and were successful in the formation of a desired concavity by using an etching hole of a pattern shape extending in the  less than 110 greater than  direction.
Namely, after forming a dielectric film having first and second etching holes on the entire surface of a semiconductor substrate, the semiconductor substrate is dipped into an etching solution. Then, the surface of the semiconductor substrate exposed by the etching holes is etched toward the (100) surface. By providing sides (tilted by 45xc2x0 in an embodiment) tilted in the  less than 110 greater than  and  less than xe2x88x92110 greater than  directions, etching proceeds toward a surface that is in parallel with the sides. By this means, a part of imaginary rectangle shape is removed by the etching.
Then, because the imaginary rectangle is formed such that these imaginary rectangles are directly or indirectly continuous, the region removed due to the first etching hole and the region removed due to the second etching hole are connected. Then, the (411) surface appears. As a result, as explained in detail in the embodiment, etching proceeds toward this (411) surface in a high speed. In other words, etching advances substantially from the part at the point of intersection of the first and second etching holes. By doing this, a concavity in a rectangular shape having sides that is perpendicular and parallel with the  less than 110 greater than  direction is formed. Because of the use of a highest speed etching of the (411) surface, a concavity can be formed over a shorter time period than using a conventional technology.
Then, due to formation of the first and second etching holes extending in the  less than 110 greater than  direction and  less than xe2x88x92110 greater than  direction, the part of the dielectric film facing the concavity is divided into rectangles by these etching holes. As a result, wiring becomes simple, yield is increased, and manufacturing is easy without causing cutting of the wiring pattern.
Here, xe2x80x9cimaginary rectangles that directly connectxe2x80x9d means that the imaginary rectangles based upon each first and second etching hole contact to each other (either linear contact or point contact), or partially overlaps to each other. Also, xe2x80x9cimaginary rectangles that indirectly connectxe2x80x9d means that the imaginary rectangles are connected to each other via another etching hole that is separately provided.
Preferably, the first and second etching holes intersect at the center of the concavity. A concavity can be formed over a short time period since etching proceeds toward the perimeter from the intersection part. Because the regions on the dielectric film divided by each of the etching holes are maintained equally symmetrically, that balance is good, and layout of wiring can be easily carried out.
Another etching hole may be provided at the intersecting part of the first etching hole and the second etching hole. It becomes possible to form the concavity more rapidly when an etching hole is provided at the intersecting part. Also, the imaginary rectangle A due to the first etching hole and the imaginary rectangle B due to the second etching hole may be continuous via the imaginary rectangle (including the case of an imaginary square) due to the etching hole at the intersection part. It is not necessary that imaginary rectangle A and imaginary rectangle B be directly continuous. In other words, layout pitch can be expanded.
Also, a supplementary etching hole may be provided at the intersecting part of adjacent first etching holes or adjacent second etching holes. Depending on the pattern shape of the first and second etching holes, if the imaginary rectangles due to such holes are made to be directly continuous, adjacent first (second) etching holes may end up continuous together. In this state, there is a danger that the dielectric film be cut at such a part. Therefore, by providing a supplementary etching hole, it becomes possible to indirectly connect the imaginary rectangles due to the first and second etching holes via a region that is removed due to this supplementary etching hole.
Possible specific examples of the application of the semiconductor device of the present invention include various types of devices such as flow sensors; thermal sensors, infrared sensors, temperature sensors, or micro-heaters. As an example, the above mentioned circuit pattern can be equipped with a first heater element of a fixed specified shape for use generating heat and a second heater element that senses variation of temperature upon the above mentioned dielectric film. This invention is achieved by the embodiment shown in FIG. 17.
Moreover, the above mentioned circuit pattern as another embodiment can comprise upon the above mentioned dielectric film a first resistor element having a specified shape used for constant generation of heat and a second thermoelectric conversion element that senses change of temperature. An embodiment of this invention is indicated by the working example shown in FIG. 18.
Assuming use of the above mentioned structures, the second etching hole is preferably provided at the far end of the continuing first etching hole. By use of this structure as shown in FIG. 17-FIG. 19, the part of the dielectric film opposite the concavity is divided into rectangles by the first and second etching holes. Then if a first etching hole is provided centrally as in the working examples, this first etching hole becomes nearly equidistant from the perimeter (where the dielectric film and semiconductor wafer are joined together), and a resister element or thermoelectric conversion element can be formed over a wide surface area. Furthermore, spacing between the hot contact and the cold contact of the thermoelectric conversion element can be widened over the entire thermoelectric conversion element (it becomes possible to place a contact point in the vicinity of the center of the dielectric film), and thermal insulation can be increased between both contacts. Therefore output voltage increases (1.2 times relative to that when etching holes are laid out at the conventional 45xc2x0 angle).